FIG. 3 shows a typical digital Multiply-Accumulate circuit 50 of the prior art. Registers 52 and 54 hold two operands to be operated on. These two operands must be in the same data format, i.e. both must be either integers or floating point numbers. The two operands are multiplied in multiplier 56 and the resultant product is inputted into adder 58 as a first input. A second input of adder 58 comes from accumulator 60. The resultant sum of the two inputs generated by adder 58 will replace the current content of accumulator 60. Another pair of operands may be loaded into registers 52 and 54. Their product generated by multiplier 56 is accumulated by adder 58 into accumulator 60. So, accumulator 60 holds the sum of products of pairs of operands. For that reason, circuit 50 is also called a product adder.
A typical digital Multiply-Accumulate circuit as shown in FIG. 3 cannot operate on both integer and floating point numbers simultaneously. When a computation involves operands of both integer and floating point numbers, a separate converting circuit is used. The converting circuit may be of integer-to-floating-point type in which the integer is converted into a floating point number before being loaded into the floating point Multiply-Accumulate circuit to be multiplied with another floating point number.
FIG. 4 shows a typical Integer to Floating Point converting circuit of prior art. This circuit is disclosed and described in detail in U.S. Pat. No. 4,631,696. The 32-bit integer to be converted to floating point number is in register 11. Zero detectors Z0 to Z7 detects leading zeros of the integer. Priority encoder 13 receives the detection results from Zero detectors Z0 to Z7 and determines the necessary number of shifting places for the integer. Shifter 15 shifts the integer according to the control input LZ from priority encoder 13 producing the 24-bit mantissa. The detected number of leading zeros of the integer is used to calculate the 7-bit offset exponent using adder 14.
An object of the present invention is to provide a Multiply-Accumulate circuit that can accept operands of both integer and floating point numbers, but does not require much additional circuitry. Another object of the present invention is to use only one instruction set for operations on both integer and floating point numbers.